Address some missing operations for ECDSA.

This commit is contained in:
2018-12-23 21:05:05 -08:00
parent 6c40ee5109
commit 85165c7f68
7 changed files with 17033 additions and 0 deletions

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@@ -32,8 +32,10 @@ mul_impls!(I448, I896);
conversion_impls!(I448, U448, I896, U896); conversion_impls!(I448, U448, I896, U896);
signed_impls!(I512, U512); signed_impls!(I512, U512);
subtraction_impls!(I512, I576, U576); subtraction_impls!(I512, I576, U576);
mul_impls!(I512, I1024);
div_impls!(I512, U512); div_impls!(I512, U512);
conversion_impls!(I512, U512, I576, U576); conversion_impls!(I512, U512, I576, U576);
conversion_impls!(I512, U512, I1024, U1024);
egcd_impls!(I576, U512, I512); egcd_impls!(I576, U512, I512);
modinv_impls!(U512, I576, U576); modinv_impls!(U512, I576, U576);
add_impls!(I576, I640, U640); add_impls!(I576, I640, U640);
@@ -52,8 +54,10 @@ conversion_impls!(I640, U640, I1280, U1280);
signed_impls!(I704, U704); signed_impls!(I704, U704);
signed_impls!(I896, U896); signed_impls!(I896, U896);
subtraction_impls!(I896, I960, U960); subtraction_impls!(I896, I960, U960);
mul_impls!(I896, I1792);
div_impls!(I896, U896); div_impls!(I896, U896);
conversion_impls!(I896, U896, I960, U960); conversion_impls!(I896, U896, I960, U960);
conversion_impls!(I896, U896, I1792, U1792);
signed_impls!(I960, U960); signed_impls!(I960, U960);
signed_impls!(I1024, U1024); signed_impls!(I1024, U1024);
conversion_impls!(I1024, U1024, I1088, U1088); conversion_impls!(I1024, U1024, I1088, U1088);
@@ -68,8 +72,10 @@ conversion_impls!(I1088, U1088, I1152, U1152);
signed_impls!(I1152, U1152); signed_impls!(I1152, U1152);
signed_impls!(I1280, U1280); signed_impls!(I1280, U1280);
subtraction_impls!(I1280, I1344, U1344); subtraction_impls!(I1280, I1344, U1344);
mul_impls!(I1280, I2560);
div_impls!(I1280, U1280); div_impls!(I1280, U1280);
conversion_impls!(I1280, U1280, I1344, U1344); conversion_impls!(I1280, U1280, I1344, U1344);
conversion_impls!(I1280, U1280, I2560, U2560);
signed_impls!(I1344, U1344); signed_impls!(I1344, U1344);
signed_impls!(I1536, U1536); signed_impls!(I1536, U1536);
conversion_impls!(I1536, U1536, I1600, U1600); conversion_impls!(I1536, U1536, I1600, U1600);
@@ -81,6 +87,7 @@ shift_impls!(I1600, U1600);
subtraction_impls!(I1600, I1664, U1664); subtraction_impls!(I1600, I1664, U1664);
conversion_impls!(I1600, U1600, I1664, U1664); conversion_impls!(I1600, U1600, I1664, U1664);
signed_impls!(I1664, U1664); signed_impls!(I1664, U1664);
signed_impls!(I1792, U1792);
signed_impls!(I2048, U2048); signed_impls!(I2048, U2048);
conversion_impls!(I2048, U2048, I2112, U2112); conversion_impls!(I2048, U2048, I2112, U2112);
egcd_impls!(I2112, U2048, I2048); egcd_impls!(I2112, U2048, I2048);
@@ -92,6 +99,7 @@ shift_impls!(I2112, U2112);
subtraction_impls!(I2112, I2176, U2176); subtraction_impls!(I2112, I2176, U2176);
conversion_impls!(I2112, U2112, I2176, U2176); conversion_impls!(I2112, U2112, I2176, U2176);
signed_impls!(I2176, U2176); signed_impls!(I2176, U2176);
signed_impls!(I2560, U2560);
signed_impls!(I3072, U3072); signed_impls!(I3072, U3072);
conversion_impls!(I3072, U3072, I3136, U3136); conversion_impls!(I3072, U3072, I3136, U3136);
egcd_impls!(I3136, U3072, I3072); egcd_impls!(I3136, U3072, I3072);
@@ -211,9 +219,11 @@ mod tests {
generate_signed_tests!(I1536, U1536, i1536); generate_signed_tests!(I1536, U1536, i1536);
generate_signed_tests!(I1600, U1600, i1600); generate_signed_tests!(I1600, U1600, i1600);
generate_signed_tests!(I1664, U1664, i1664); generate_signed_tests!(I1664, U1664, i1664);
generate_signed_tests!(I1792, U1792, i1792);
generate_signed_tests!(I2048, U2048, i2048); generate_signed_tests!(I2048, U2048, i2048);
generate_signed_tests!(I2112, U2112, i2112); generate_signed_tests!(I2112, U2112, i2112);
generate_signed_tests!(I2176, U2176, i2176); generate_signed_tests!(I2176, U2176, i2176);
generate_signed_tests!(I2560, U2560, i2560);
generate_signed_tests!(I3072, U3072, i3072); generate_signed_tests!(I3072, U3072, i3072);
generate_signed_tests!(I3136, U3136, i3136); generate_signed_tests!(I3136, U3136, i3136);
generate_signed_tests!(I3200, U3200, i3200); generate_signed_tests!(I3200, U3200, i3200);
@@ -250,9 +260,11 @@ mod tests {
generate_sigconversion_tests!(I1536, U1536, i1536); generate_sigconversion_tests!(I1536, U1536, i1536);
generate_sigconversion_tests!(I1600, U1600, i1600); generate_sigconversion_tests!(I1600, U1600, i1600);
generate_sigconversion_tests!(I1664, U1664, i1664); generate_sigconversion_tests!(I1664, U1664, i1664);
generate_sigconversion_tests!(I1792, U1792, i1792);
generate_sigconversion_tests!(I2048, U2048, i2048); generate_sigconversion_tests!(I2048, U2048, i2048);
generate_sigconversion_tests!(I2112, U2112, i2112); generate_sigconversion_tests!(I2112, U2112, i2112);
generate_sigconversion_tests!(I2176, U2176, i2176); generate_sigconversion_tests!(I2176, U2176, i2176);
generate_sigconversion_tests!(I2560, U2560, i2560);
generate_sigconversion_tests!(I3072, U3072, i3072); generate_sigconversion_tests!(I3072, U3072, i3072);
generate_sigconversion_tests!(I3136, U3136, i3136); generate_sigconversion_tests!(I3136, U3136, i3136);
generate_sigconversion_tests!(I3200, U3200, i3200); generate_sigconversion_tests!(I3200, U3200, i3200);
@@ -292,7 +304,10 @@ mod tests {
generate_sigmul_tests!(I256, U256, i256, I512, U512); generate_sigmul_tests!(I256, U256, i256, I512, U512);
generate_sigmul_tests!(I320, U320, i320, I640, U640); generate_sigmul_tests!(I320, U320, i320, I640, U640);
generate_sigmul_tests!(I448, U448, i448, I896, U896); generate_sigmul_tests!(I448, U448, i448, I896, U896);
generate_sigmul_tests!(I512, U512, i512, I1024, U1024);
generate_sigmul_tests!(I640, U640, i640, I1280, U1280); generate_sigmul_tests!(I640, U640, i640, I1280, U1280);
generate_sigmul_tests!(I896, U896, i896, I1792, U1792);
generate_sigmul_tests!(I1280, U1280, i1280, I2560, U2560);
} }
mod sigdiv { mod sigdiv {
use super::super::*; use super::super::*;

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@@ -67,6 +67,7 @@ needs = [ Need RSA (\ size -> [Req (size `div` 2) Sub,
Req (size + 64) SignedMul, Req (size + 64) SignedMul,
Req ((size + 64) * 2) SignedSub, Req ((size + 64) * 2) SignedSub,
Req ((size + 64) * 2) SignedDiv, Req ((size + 64) * 2) SignedDiv,
Req ((size + 64) * 2) SignedMul,
Req size (Convert ((size + 64) * 2)), Req size (Convert ((size + 64) * 2)),
Req size (SigConvert ((size + 64) * 2)) Req size (SigConvert ((size + 64) * 2))
]) ])

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testdata/sigmul/00512.test vendored Normal file

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testdata/sigmul/00896.test vendored Normal file

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testdata/sigmul/01280.test vendored Normal file

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testdata/signed/01792.test vendored Normal file

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testdata/signed/02560.test vendored Normal file

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